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DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 8 channel serial interface low-side driver check for samples: DRV8860 1 features applications ? 8-channel protected low-side driver ? relays ? eight nmos fets with overcurrent ? unipolar stepper motors protection ? solenoids ? integrated inductive catch diodes ? electromagnetic drivers ? open/short load detection ? general low-side switch applications ? configurable 100% output timing description ? configurable pwm duty cycle the DRV8860 provides an 8-channel low side driver ? continuous current driving capability with overcurrent protection and open/shorted load ? 560ma (single channel on) detection. it has built-in diodes to clamp turn-off ? 280ma (quad channels on) transients generated by inductive loads, and can be used to drive unipolar stepper motors, dc motors, ? 200ma (oct channels on) relays, solenoids, or other loads. ? support parallel configuration DRV8860 can supply up to 200ma 8 channel ? 8v to 38v supply voltage range continuous output current. the current driving ? input digital noise filter for noise immunity capability increased with lower pwm duty cycle. a ? internal data read back capability for reliable single channel can deliver up to 560ma continuous output current. refer to the output current control recommendation section for details. ? programmable current profile a serial interface is provided to control the DRV8860 ? configurable 100% output timing. fast output drivers, configure internal setting register and activation of solenoid. read the fault status of each channel. multiple ? configurable pwm duty cycle in chopping DRV8860 devices can be daisy-chained together to mode. reducing power consumption and use a single serial interface. energizing-time and thermal dissipation in hold-mode of holding-pwm-duty cycles are configurable through solenoid. serial interface as well. these functions allow for lower temperature operation rather than traditional ? serial interface always-on solutions. ? daisy chain connection internal shutdown functions are provided for over ? 16-pin tssop package current protection, short circuit protection, under ? protection and diagnostic features voltage lockout, and over temperature. DRV8860 can ? overcurrent protection (ocp) diagnosis the open load condition. fault information for each channel can be read out through serial ? open load detection (ol) interface and indicated by an external fault pin. ? over-temperature shutdown (ots) the DRV8860 is packaged in a 16 pin tssop ? under-voltage lockout (uvlo) package (eco-friendly: rohs and no sb/br). ? individual channel status report ? fault condition alarm ordering information for the most current packaging and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . the package drawings, thermal data, and symbolization are available at www.ti.com/packaging . 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. functional block diagram 2 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860 gnd 8 ~38 v 10 f vm vm internal reference regulators uvlo 4.5 v nfault enable pwm logic vm gate drive, ocp, ol out1 vm gate drive, ocp, ol out2 vm gate drive, ocp, ol out3 vm gate drive, ocp, ol out4 vm gate drive, ocp, ol out5 vm gate drive, ocp, ol out6 vm gate drive, ocp, ol out7 vm gate drive, ocp, ol out8 control logic and registers temperature sensor and thermal shutdown 8 ~38 v latch din clk dout serial interface 0.1f
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 pw (tssop) package (top view) pin functions name pin i/o (1) description external components or connections power and ground gnd 5 ? device ground all pins must be connected to ground connect to motor supply voltage. bypass to gnd with a 0.1 f ceramic capacitor vm 1 ? motor power supply plus a 10 f electrolytic capacitor. control and serial interface output stage enable logic high to enable outputs, logic low to disable outputs. internal logic and enable 8 i control input registers can be read and written to when enable is logic low. internal pulldown. latch 4 i serial latch signal refer to serial communication waveforms. internal pulldown. rising edge clocks data into part for write operations. falling edge clocks data out clk 3 i serial clock input of part for read operations. internal pulldown. din 2 i serial data input serial data input from controller. internal pulldown. dout 6 o serial data output serial data output to controller. open-drain output with internal pullup. status logic low when in fault condition. open-drain output requires external pullup. nfault 7 od fault faults: ocp, ol, ots, uvlo output out1 16 o low-side output 1 nfet output driver. connect external load between this pin and vm out2 15 o low-side output 2 nfet output driver. connect external load between this pin and vm out3 14 o low-side output 3 nfet output driver. connect external load between this pin and vm out4 13 o low-side output 4 nfet output driver. connect external load between this pin and vm out5 12 o low-side output 5 nfet output driver. connect external load between this pin and vm out6 11 o low-side output 6 nfet output driver. connect external load between this pin and vm out7 10 o low-side output 7 nfet output driver. connect external load between this pin and vm out8 9 o low-side output 8 nfet output driver. connect external load between this pin and vm (1) directions: i = input, o = output, oz = tri-state output, od = open-drain output, io = input/output critical components pin name component 10 f electrolytic rated for vm voltage to gnd, 1 vm 0.1 f ceramic rated for vm voltage to gnd 7 nfault requires external pullup to logic supply copyright ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: DRV8860 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vm din clk latch gnd dout enable nfault out1 out2 out3 out4 out5 out6 out7 out8
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) DRV8860 unit min max power supply voltage range (vm) ? 0.3 40 v digital input pin current range (enable, latch, clk, din) 0 20 ma digital output pin voltage range (dout, nfault) ? 0.5 7 v digital output pin current (dout, nfault) ? 0.5 7 v output voltage range (outx) ? 0.3 40 v output current range (outx) internally limited a operating virtual junction temperature range, t j ? 40 150 c storage temperature range, t stg ? 60 150 c (1) stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) power dissipation and thermal limits must be observed thermal information (1) over operating free-air temperature range (unless otherwise noted) DRV8860 thermal metric units pw (16 pins) ja junction-to-ambient thermal resistance (2) 103 jc(top) junction-to-case (top) thermal resistance (3) 37.9 jb junction-to-board thermal resistance (4) 48 c/w jt junction-to-top characterization parameter (5) 3 jb junction-to-board characterization parameter (6) 47.4 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) the junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a jedec-standard, high-k board, as specified in jesd51-7, in an environment described in jesd51-2a. (3) the junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. no specific jedec standard test exists, but a close description can be found in the ansi semi standard 30-88. (4) the junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. (5) the junction-to-top characterization parameter, jt , estimates the junction temperature of the device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (6) the junction-to-board characterization parameter, jb , estimates the junction temperature of the device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v m motor power supply voltage range 8.2 38 v i out low-side driver current capability 560 ma t a operating ambient temperature range ? 40 85 c 4 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 electrical characteristics t a = 25 c, over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit power supplies i vm vm operating supply current vm = 24v 3 ma v uvlo vm undervoltage lockout voltage vm rising 8.2 v logic-level inputs (din, clk, latch, enable) v il input low voltage 0.6 0.7 v v ih input high voltage 2 v v hys input hysteresis 0.45 v i il input low current vin = 0 ? 20 20 a i ih input high current vin = 3.3v 100 a r pd input pulldown resistance 100 k nfault, dout outputs (open-drain outputs) v ol output low voltage i o = 5ma 0.5 v i oh output high leakage current v o = 3.3v, nfault ? 1 1 a r pu input pullup resistance dout only (pull up to internal 5.7v) 1.4 k low-side fet drivers v m = 24v, i o = 150ma, t j = 25 c 1.5 r ds(on) fet on resistance v m = 24v, i o = 150ma, t j = 85 c 1.8 i off off-state leakage current v m = 24v, t j = 25 c 0 30 a high-side free-wheeling diodes v f diode forward voltage v m = 24v, i o = 150ma, t j = 25 c 0.9 v outputs t r rise time 50 300 ns i o = 150ma, vm = 24v, resistive load tf fall time 50 300 ns protection circuits i ocp overcurrent protection trip level each channel separately monitored 620 ma t ocp overcurrent protection deglitch time vm = 24v 2.7 3.5 3.85 s iol open load detect pull-down current each channel separately monitored 30 a v ol open load detect threshold voltage each channel separately monitored 1.2 v t ol open load detect deglitch time each channel separately monitored 14 17 20 s t tsd thermal shutdown temperature die temperature 150 160 180 c t hys thermal shutdown hysteresis die temperature 35 c pwm chopping frequency duty cycle is > 25% 45 50 55 f pwm pwm chopping frequency duty cycle is 25% 22 25 28 khz duty cycle is 12.5% 11 12.5 14 copyright ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com output current recommendation DRV8860 current capability will depend on several system application parameters: ? system ambient temperature ? maximum case temperature ? overall output current duty cycle ? output channel configuration output current recommendation (pw package) t a = 25 c configuration output current capacity 1x output on (100% duty cycle) 566ma 2x outputs on (100% duty cycle) 400ma per output 4x outputs on (100% duty cycle) 283ma per output 8x outputs on (100% duty cycle) 200ma per output 6 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 copyright ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com daisy chain connection two or more drv8806 devices may be connected together to use a single serial interface. the dout pin of the first device in the chain is connected to the din pin of the next device. the sclk, latch, reset, and nfault pins are connected together. timing diagrams are shown on the following pages for the configuration of single devices, as well as two devices in daisy-chain connection. single device connection daisy-chain connection 8 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860 host processor DRV8860 latch din clk dout nfault out1 8 ~38 v gpio gpio gpio gpio gpio out8 host processor DRV8860 device #1 latch din 1 clk dout 1 out1 8 ~38 v gpio gpio gpio gpio out8 DRV8860 device #2 latch din 2 clk dout 2 out1 out8
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 example output configuration example configuration 1: DRV8860 drives 8 low side loads example configuration 2: DRV8860 drives multiple low side loads with parallel configuration example configuration 3: DRV8860 drives two unipolar stepper motors copyright ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: DRV8860 host processor DRV8860 latch din clk dout nfault out2 gpio gpio gpio gpio gpio out8 out1 out3 out4 out5 out6 out7 stepper 8 ~38 v 8 ~38 v stepper 8 ~38 v 8 ~38 v host processor DRV8860 latch din clk dout nfault out2 8 ~38 v gpio gpio gpio gpio gpio out8 out1 out3 out4 out5 out6 out7 host processor DRV8860 latch din clk dout nfault out2 8 ~38 v gpio gpio gpio gpio gpio out8 out1 out3 out4 out5 out6 out7
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com functional description internal registers the DRV8860 is controlled with a simple serial interface. there are three register banks that are used during operation: the data register, the control register, and the fault register. register data movement flow and direction will be affected by special command. in default condition, 8 bit shift register data moves into output control register data-reg 10 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 copyright ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com data register the data register is used to control the status of each of the eight outputs: data register d8 d7 d6 d5 d4 d3 d2 d1 out8 out7 out6 out5 out4 out3 out2 out1 when any bit is ? 1 ? , the corresponding output will be active. when any bit is ? 0 ? , the output will be inactive. the data register is the default write location for the serial interface. in order to read back data from this register, the data register readout special command is used. fault register the fault register can be read to determine if any channel exist fault condition. ocp is an over current fault and ol is an open load fault. fault register f16 f15 f14 f13 f12 f11 f10 f9 out8 ocp out7 ocp out6 ocp out5 ocp out4 ocp out3 ocp out2 ocp out1 ocp spacer f8 f7 f6 f5 f4 f3 f2 f1 out8 ol out7 ol out6 ol out5 ol out4 ol out3 ol out2 ol out1 ol when any fault occurs, nfault pin will be driven low and corresponding fault register bit will be set up as ? 1 ? . ocp is a flag indicating over current fault. ol is a flag indicating open load fault. fault bits can be reset by two approaches: 1. special command ? fault reset ? clear all fault bits. 2. setting data register to on will clear corresponding ol bits. setting data register to off will clear corresponding ocp bits. control register the control register is used to adjust the energizing time and pwm duty cycle of outputs: control register c8 c7 c6 c5 c4 c3 c2 c1 over all enable pwm duty cycle control energizing time control special command ? write control register ? is used to program control register. special command ? read control register ? is used to read back control register content. 12 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 serial control interface DRV8860 is using a daisy chain serial interface. data shifting control is enabled by a falling edge of latch pin. data is latched into the register on the rising edge of the latch pin. data is clocked in on the rising edge of clk when writing, and data is clocked out on the falling edge of clk when reading. data writing waveform copyright ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com fault register reading waveform 14 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 special command besides output on/off control and fault status reading back, DRV8860 has special functions to make system more robust or power efficient. these functions will need special command to initiate the device or configure the internal registers. there are 5 special commands: 1. write control register command 2. read control register command 3. read data register command 4. fault register reset command 5. pwm start command special wave form pattern on clk and latch pin will issue the special command, as below clk cycles in each part special command part i part ii part iii part iv write control register 1 2 2 3 read control register 1 4 2 3 read data register 1 4 4 3 fault register reset 1 2 4 3 pwm start 1 6 6 3 copyright ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com special command: write control register when write-control-register command is issued, the following serial data will be latched into timing and duty control register. 16 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 special command: read control register when read-control-register command is issued, control register content will be copied to internal shift register and following clk will shift this content out from dout pin. this provides a mechanism for system to verify the control register is correctly programmed. copyright ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com special command: read data register when read-data-register command is issued, internal output data register content will be copied to internal shift register and following clk will shift this content out from dout pin. this provides a mechanism for system to verify the output data is correctly programmed. it makes system more robust in noisy system. 18 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 special command: fault register reset when fault-register-reset command is issued, internal 16bit fault register will be cleared. system can use this method to clear out all fault condition in every chained device at once. special command: pwm start when fault-register-reset command is issued, output channel will ignore energizing time and directly enter into pwm mode following the setting in control register. copyright ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com output energizing and pwm control the device output is defined by two stages: energizing phase and pwm phase. this special feature is designed to save energy and reduce heat for electromagnetic armature loads. it as well can be used to adjust average output voltage for resistance load. during the energizing phase, the channel is turned on with 100% duty cycle for a duration set by control register bits c4:c1. in pwm chopping phase, with the pwm duty cycle defined by control register bits c7:c5. the behavior of each bit in the control register is described in the table below: control register settings c8 c7 c6 c5 c4 c3 c2 c1 value description 0 x x x x x x x n/a outputs always in energizing mode 1 x x x 0 0 0 0 0 ms no energizing, starts in pwm chopping 1 x x x 0 0 0 1 3 ms 1 x x x 0 0 1 0 5 ms 1 x x x 0 0 1 1 10 ms 1 x x x 0 1 0 0 15 ms 1 x x x 0 1 0 1 20 ms 1 x x x 0 1 1 0 30 ms 1 x x x 0 1 1 1 50 ms sets the energizing time (100% duty cycle) before 1 x x x 1 0 0 0 80 ms switching to pwm phase 1 x x x 1 0 0 1 110 ms 1 x x x 1 0 1 0 140 ms 1 x x x 1 0 1 1 170 ms 1 x x x 1 1 0 0 200 ms 1 x x x 1 1 0 1 230 ms 1 x x x 1 1 1 0 260 ms 1 x x x 1 1 1 1 300 ms 1 0 0 0 x x x x 0% output is off after energizing phase 1 0 0 1 x x x x 12.50% 12.5 khz 1 0 1 0 x x x x 25.00% 25 khz 1 0 1 1 x x x x 37.50% sets pwm chopping duty cycle. dc is the 1 1 0 0 x x x x 50.00% duty cycle that the low-side fet is on. 1 1 0 1 x x x x 62.50% 50 khz 1 1 1 0 x x x x 75.00% 1 1 1 1 x x x x 87.50% 20 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 different operation cases with inductive load are described in following pages. case 1: timer enable bit (c8) is 0 (default value) the output is turned on with 100% duty cycle. case 2: timer enable bit (c8) is 1 and energizing timing bits (c4:c1) are 0000 the output is turned on in pwm chopping mode with duty cycle defined by control register bits c7:c5. copyright ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: DRV8860 outx voltage (v) time (ms) vm outx current (ma) time (ms) dc*vm/r l pwm chopping
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com case 3: timer enable bit (c8) is 1, energizing timing bits (c4:c1) are not 0000, and pwm duty bits (c7:c5) are not 000 the output is turned on in energizing mode with 100% duty cycle for a duration set by control register bits c4:c1. after the timer expires, the output switches to pwm chopping mode with pwm duty cycle defined by control register bits c7:c5. case 4: timer enable bit (c8) is 1, energizing timing bits (c4:c1) are not 0000, and pwm duty bits (c7:c5) are 000 the output is turned on in energizing mode with 100% duty cycle for a duration set by control register bits c4:c1. after the timer expires, the output is turned off. 22 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 case 5: timer enable bit (c8) is 0, energizing timing bits (c4:c1) are not 0000, and pwm duty bits (c7:c5) are not 000 pwm start special command used the output is turned on in energizing mode with 100% duty cycle, and a timer is enabled with duration set by control register bits c4:c1. if the pwm start special command is received before the timer expires, then the output switches to pwm chopping mode with pwm duty cycle defined by control register bits c7:c5. if the timer expires and no pwm start is received, then the device will stay in energizing mode regardless of other pwm start commands. copyright ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: DRV8860
DRV8860 slrs065a ? september 2013 ? revised november 2013 www.ti.com protection circuits the DRV8860 is fully protected against undervoltage, overcurrent and overtemperature events. overcurrent protection (ocp) when output current exceeds ocp trigger level, corresponding channel will be automatically turned off. nfault pin will be set low and corresponding ocp flag in fault register will be set to 1. over current faults are automatically cleared whenever the corresponding output is turned off by setting the data register bit to ? 0 ? . alternatively, a fault reset special command will also clear this value. in either case, once all bits in the fault register are clear, nfault is released. open load detection (ol) when any output is in off status (the corresponding data register bit is set to ? 0 ? ), a current sink pulls the node down with approximately 30 a. if the voltage on the pin is sensed to be less than 1.2 v, then an open load condition is reported. nfault is driven low and the ol bit of the fault register (f8:f1) corresponding to the specific channel is set. open load faults are automatically cleared whenever the corresponding output is turned on by setting the data register bit to ? 1 ? . alternatively, a fault reset special command will also clear this value. in either case, once all bits in the fault register are clear, nfault is released. thermal shutdown (tsd) if the die temperature exceeds safe limits, all outputs will be disabled, and the nfault pin will be driven low. once the die temperature has fallen to a safe level, operation will automatically resume. the nfault pin will be released after operation has resumed. undervoltage lockout (uvlo) if at any time the voltage on the vm pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. operation will resume when vm rises above the uvlo threshold. nfault will not be asserted in this condition. digital noise filter the DRV8860 features an internal noise filter on all digital inputs. in a noisy system, noise may disturb the serial daisy-chain interface. without an input filter, this noise may result in an unexpected behavior or output state. the digital input filter is capable of removing unwanted noise frequencies while allowing fast communication over the serial interface. 24 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: DRV8860
DRV8860 www.ti.com slrs065a ? september 2013 ? revised november 2013 revision history changes from original (september 2013) to revision a page ? added additional features. .................................................................................................................................................... 1 ? updated min value for v m in the recommended operating conditions table. .................................................................... 4 ? added example output configuration section. ..................................................................................................................... 9 copyright ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: DRV8860
package option addendum www.ti.com 8-nov-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples DRV8860pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 8860 DRV8860pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 8860 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 8-nov-2013 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant DRV8860pwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 8-nov-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) DRV8860pwr tssop pw 16 2000 367.0 367.0 35.0 package materials information www.ti.com 8-nov-2013 pack materials-page 2

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